Full-Chip STA Signoff Engineer
- Work arrangement
- On-site
- Occupation
- Software & IT
- Location
- Hyderabad, Telangana, India
- Compensation
- INR 1,400,000.00 – INR 3,200,000.00 per year
- Apply by
- April 10, 2027
About this role
This role is for one of Weekday’s clients
Salary range: Rs 1400000 - Rs 3200000 (ie INR 14 - 32 LPA)
Min Experience: 6+ years
Location: Hyderabad
JobType: full-time
We are looking for an experiencedFull-Chip STA Signoff Engineerwith 6–17 years of hands-on experience in Static Timing Analysis and timing closure for complex SoC designs. The ideal candidate will have strong expertise infull-chip STA signoff, timing analysis, constraint development, timing closure, and signoff methodologies across advanced semiconductor process nodes.
You will work closely with RTL, synthesis, physical design, clock, and implementation teams to analyze timing, identify critical paths, resolve timing violations, and ensure the design meets all timing requirements before tapeout.