FPGA Engineer - Chip Design

<h3>Accountabilities:</h3><li>Develop realistic engineering evaluation tasks spanning RTL design, functional verification, logic synthesis, physical design, and sign-off.</li><li>Create high-quality reference implementations using Verilog, SystemVerilog, or VHDL, supported by testbenches, design constraints, expected outputs, and validation procedures.</li><li>Establish clear grading criteria and assessment methodologies that reflect industry-standard chip-design practices and engineering expectations.</li><li>Evaluate AI-generated RTL code, testbenches, hardware designs, and implementation results to identify functional errors, architectural weaknesses, and design inefficiencies.</li><li>Diagnose verification failures, coverage gaps, timing violations, and suboptimal power, performance, and area (PPA) trade-offs.</li><li>Assess hardware designs based on functional correctness, timing requirements, resource utilization, implementation quality, and overall design robustness.</li><li>Configure, maintain, and improve electronic design automation (EDA) environments that enable AI agents to execute realistic chip-design workflows.</li><li>Apply relevant industry tools and workflows, including Synopsys, Cadence, Siemens, AMD/Xilinx Vivado, and Intel Quartus, depending on the evaluation requirements.</li><li>Design evaluation scenarios covering synthesis quality, place-and-route outcomes, static timing analysis, timing constraints, and timing closure.</li><li>Identify recurring failure patterns in AI-generated designs and translate them into new test cases, evaluation scenarios, and more challenging engineering benchmarks.</li><li>Collaborate with engineering and research teams to improve evaluation frameworks, testing strategies, technical benchmarks, and overall assessment quality.</li><li>Automate design workflows, testing procedures, and results analysis using scripting languages such as Python, Tcl, or Perl.</li><li>Document reference designs, engineering assumptions, known failure cases, evaluation criteria, and methodologies to ensure reproducibility and consistency.</li><h2>Requirements:</h2><li>Have at least 3 years of relevant professional experience, with approximately 3–5 years of hands-on ASIC or FPGA design experience preferred, ideally covering multiple stages of the digital design lifecycle.</li><li>Hold a B.E., B.Tech, or M.Tech degree in Electrical Engineering, Electronics Engineering, VLSI, or a related technical discipline.</li><li>Demonstrate strong RTL development skills in Verilog, SystemVerilog, or VHDL, with the ability to develop reliable, maintainable, and functionally correct hardware designs.</li><li>Have practical experience in digital design verification, including testbench development, debugging, coverage analysis, and methodologies such as UVM or equivalent verification approaches.</li><li>Possess working knowledge of industry-standard EDA tools and workflows, including platforms from Synopsys, Cadence, Siemens, AMD/Xilinx, or Intel.</li><li>Understand logic synthesis, physical design, place-and-route, static timing analysis, timing constraints, and timing closure.</li><li>Demonstrate sound engineering judgment when evaluating PPA trade-offs, implementation quality, resource utilization, and design feasibility.</li><li>Have experience taking at least one chip-design project from specifications through implementation or tape-out, with a solid understanding of the associated engineering challenges.</li><li>Possess strong analytical, debugging, and problem-solving skills, including the ability to identify root causes and clearly explain why a design succeeds or fails.</li><li>Be capable of developing structured technical assessments, defining objective evaluation criteria, and documenting findings with precision.</li><li>Have familiarity with Python, Tcl, or Perl for scripting, workflow automation, and engineering data analysis; experience with these tools is an advantage.</li><li>Have exposure to open-source hardware design and verification tools such as Yosys, OpenROAD, Verilator, or cocotb, which is beneficial.</li><li>Demonstrate an interest in AI engineering evaluations, reinforcement-learning environments, or model post-training; previous experience in these areas is a plus but not mandatory.</li><li>Be comfortable working independently in a remote environment while collaborating effectively with multidisciplinary engineering and research teams.</li><h2>Benefits:</h2><li>
<strong>Competitive salary:</strong>INR 12,00,000–20,00,000 per year (12–20 LPA), depending on experience and qualifications.</li><li>
<strong>Fully remote work:</strong>Work remotely from India, offering flexibility without a required office-based arrangement.</li><li>
<strong>Full-time opportunity:</strong>A full-time position focused on advanced semiconductor engineering and AI-driven chip-design evaluation.</li><li>
<strong>Cutting-edge technical exposure:</strong>Apply ASIC and FPGA design expertise to emerging AI systems, engineering evaluations, and automated hardware-design workflows.</li><li>
<strong>End-to-end design experience:</strong>Work across RTL development, verification, synthesis, physical implementation, and timing analysis.</li><li>
<strong>Research and engineering collaboration:</strong>Partner with technical teams to improve AI evaluation methodologies, design benchmarks, and testing environments.</li><li>
<strong>Professional growth:</strong>Strengthen expertise in hardware design, verification, EDA workflows, automation, and PPA optimization.</li><li>
<strong>Additional benefits:</strong>Specific details regarding healthcare coverage, paid leave, bonuses, equipment allowances, and other employment perks have not been provided and should be confirmed during the hiring process.</li>